1. Technical Field
The present invention relates to a semiconductor substrate, to a semiconductor device, to a method of manufacturing a semiconductor substrate, and to a method of manufacturing a semiconductor device. In particular, the invention relates to a technique suitably applicable to field effect transistors formed on an SOI (silicon on insulator) substrate.
2. Related Art
Field effect transistors formed on an SOI substrate have drawn attention in terms of ease of element separation, latch-up free property, small source/drain junction capacitance, and so on. In particular, since a fully depleted SOI transistor has features, such as low power consumption, high-speed operation, and low-voltage driving, research for operating an SOI transistor in the fully depletion mode has been actively carried out. Here, the thicknesses of a BOX layer are different from each other in a channel region and in source/drain regions, which makes it possible to improve characteristics of the SOI transistor.
For example, the BOX layer is formed to have a smaller thickness below the channel region, which makes it possible to suppress a short channel effect. In addition, it is possible to reduce the amount of charges generated from a buried oxide film by radiating, for example, alpha-rays, in order to improve the reliability of a device in operation. On the other hand, the BOX layer is formed to have a larger thickness below the source/drain regions, which makes it possible to reduce parasitic capacitance of the source/drain regions. As a result, a high-speed operation can be achieved at a low voltage.
As a method of forming the BOX layer having a small thickness below the channel region and a large thickness below the source/drain regions, a method using a SIMOX (separation by implanted oxygen) technique has been disclosed in Japanese Unexamined Patent Application Publication Nos. 7-335898 and 7-78994.
That is, in the method disclosed in Japanese Unexamined Patent Application Publication No. 7-335898, an oxygen-ion implanting process and an annealing process are performed on a semiconductor substrate to form a BOX layer. In this case, when the annealing process is performed on the semiconductor substrate having oxygen ions implanted thereinto, an oxidation shielding mask is selectively formed on the semiconductor substrate, and a thermal oxidation treatment is performed thereon at a temperature of higher than 1150° C. for several hours. Then, an oxide film in a region not covered with the oxidation shielding mask grows, so that the thickness of the BOX layer becomes large in the region. However, the oxidation film in the other region covered with the oxidation shielding mask does not grow, so that the thickness of the BOX layer becomes smaller in this region.
Further, in the method disclosed in Japanese Unexamined Patent Application Publication No. 7-78994, a BOX layer having a non-uniform thickness is prepared by changing energy required for implanting oxygen ions. In this method, a thin oxide film is formed below a channel region before a field oxide film is formed. Then, after a gate electrode is formed, a thick oxide film is formed below a diffusion layer.
However, the method disclosed in Japanese Unexamined Patent Application Publication Nos. 7-335898 has problems in that oxygen ions should be implanted into the semiconductor substrate with a dosage of 1E17 to 1E18 cm−2 and a longer manufacturing time and a high manufacturing cost are required. In addition, in order to manufacture the BOX layer, high-temperature annealing should be performed for a long time, and defects may occur in an Si single crystal layer.
Furthermore, the method disclosed in Japanese Unexamined Patent Application Publication No. 7-78994 has problems in that oxygen ions should be implanted into the semiconductor substrate with a dosage of larger than 1E18 cm−2 and a longer manufacturing time and a high manufacturing cost are required. In addition, after a gate electrode is formed, annealing is performed thereon at a high temperature of about 1200° C. Therefore, redistribution of impurities occurs, and stress is applied to a gate oxide film and an Si single crystal layer.